VLSI Implementation of Area-Error Optimized Compressor-Based Modified Wallace Tree Multiplier
A Balamanikandan, K. Suresh, D Gnanaprakasam, K. Saranya
Abstract
Approximate multiplier designs can improve their energy efficiency and performance with only a slight loss in accuracy by using approximate arithmetic circuits. This method is appropriate for applications where an approximative answer is acceptable because it uses a range of calculation approaches to those priorities, returning a potentially erroneous result above one that is assured to be exact. The basic idea underlying approximate computing is that, while accurate calculation may require a lot of resources, bounded approximation can result in considerable speed and energy efficiency advantages without sacrificing accuracy. The approximate 4:2 compressor and exact compressors, as well as half adders and full adders, make up the proposed approximate multiplier. The steps of the multiplier architecture are optimised using the recently suggested modified Wallace Tree Multiplier Architecture. When compared to previous designs, the proposed multiplier architecture can generate outcomes with the least amount of inaccuracy. The multiplier architecture is also finished in just two steps. The Modified Wallace Tree Architecture used in the suggested approximate multiplier excels by providing an error rate of 71.80% and a mean error of 173.82. As a result, the mean * error Product improved by 10%, the error rate improved by 23.3%, and the mean error increased by 31.04%. This is accomplished by the proposed approximate multiplier with a small increase of 22.36% in total power consumption.