A Scalable Design of Multi-Bit Ferroelectric Content Addressable Memory for Data-Centric Computing
Chao Li, Franz Müller, Tarek Ali, Ricardo Olivo, Mohsen Imani, Shan Deng, Cheng Zhuo, Thomas Kämpfe, Xunzhao Yin, Kai Ni
Abstract
Content addressable memory (CAM) is widely used for data-centric computing for its massive parallelism and pattern matching capability. Though the CAM density has been improved by replacing the area-consuming SRAM with compact emerging nonvolatile memories (NVMs), its implementation has been limited to single level cell. To further boost the CAM density for data-intensive workloads, exploiting the multi-level cell NVMs is highly desirable. In this work, we demonstrate: 1) a novel scalable and ultra-compact multi-bit 2FeFET1T CAM design based on two ferroelectric FETs (FeFETs) and one transistor; 2) successful operations of the proposed CAM cell and array in experiment based on 2-bit FeFET memory, and sufficient sensing margin for an 1x32 CAM array through statistical analysis considering the device variation; 3) 22.6x area per bit saving compared with SRAM CAM; 4) 16x search speedup, and 29x reduction in energy delay product over the SRAM CAM approach in accelerating a database query processing application.