First demonstration of 3-dimensional stacked FET with top/bottom source-drain isolation and stacked n/p metal gate
Jaehyun Park, Wu-Kang Kim, Sung-Il Park, Jinchan Yun, Kyu‐Man Hwang, Jinwook Yang, Dahye Kim, Jae Won Jeong, Chuljin Yun, Jinho Bae, Jejune Park, Sam Park, Woong Huh, Daihong Huh, Suk Yang, Jung-Han Lee, Jaehoon Seo, Ajeong Kim, Kyungseok Oh, Dong‐Gon Yoo, Bong Jin Kuh, Daewon Ha, Yu Gyun Shin, Jaihyuk Song
Abstract
We report world’s first demonstration of n- and pMOSFET in 3-Dimensional Stacked FET (3DSFET) with vertically stacked n/p metal gate and isolated source/drain between top and bottom FETs. We proved the possibility of 3DSFET with respect to area scaling not only by vertically stacking but also by reducing gate pitch down to 45 nm, which is the smallest dimension reported so far in 3DSFETs. The electrical properties of top/bottom placement has been studied to guide 3DSFET scheme design. Moreover, novel properties of 3DSFET has been analyzed to see the effect on threshold voltage with stacked n/p work function metal and to find the criteria for electrical isolation in terms of isolation thickness between stacked transistors.