Sub-0.5 nm Interfacial Dielectric Enables Superior Electrostatics: 65 mV/dec Top-Gated Carbon Nanotube FETs at 15 nm Gate Length
Gregory Pitner, Zichen Zhang, Qing Lin, Sheng‐Kai Su, Carlo Gilardi, Chihping Kuo, Harshil Kashyap, T. Weiß, Zhouchangwan Yu, Tzu‐Ang Chao, Lain‐Jong Li, Subhasish Mitra, H.‐S. Philip Wong, J. Cai, Andrew C. Kummel, Prabhakar R. Bandaru, M. Passlack
Abstract
To realize superior electrostatic control, a gate oxide bilayer for carbon nanotubes (CNT) is employed consisting of a 0.35 nm interfacial dielectric (k=7.8) and 2.5 nm high-k ALD dielectric (k=24). Using experimentally measured dielectric constants on sp <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> carbon and minimum oxide thickness on CNT, a COX on CNT of 2.94×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-10</sup> F/m is calculated for top-gate geometry. Gate leakage sub-1 pA/CNT is measured at 0.7V, better than the sub-5 nm node technology target. Top-gated carbon nanotube field effect transistors in this paper have 65 mV/dec subthreshold slope and DIBL as low as 20 mV/V at 15 nm gate length. Negligible hysteresis and no degradation in drive current from the top-gate process is observed. TCAD modeling predicts this approach will enable 68 mV/dec for top-gate CNFET with 10 nm L <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</inf> , 1 nm CNT diameter and 250 CNT/μm, revealing a path to energy and performance gains from a CNT transistor technology.