A PPA Study for Heterogeneous 3-D IC Options: Monolithic, Hybrid Bonding, and Microbumping
Jinwoo Kim, Lingjun Zhu, Hakki Mert Torun, Madhavan Swaminathan, Sung Kyu Lim
Abstract
In this article, we present three commercial-grade 3-D IC designs based on state-of-the-art design technologies, specifically microbumping (3-D die stacking), hybrid bonding (wafer-on-wafer bonding), and monolithic 3-D (M3D) ICs. To highlight tradeoffs present in these three designs, we perform analyses on power, performance, and area (PPA) and the clock tree. We also model the tier-to-tier interconnection in each 3-D IC methodology and analyze signal integrity (SI) to assess the reliability of each design. From our experiments using the OpenPiton benchmark, the hybrid bonding design shows the best timing improvement of 81.4% when compared to its 2-D counterpart, while microbumping shows the best reliability among 3-D IC designs. Moreover, we expand our study to the commercial processor architecture, which is Arm Cortex-A53, with the new set of 3-D integration options. In addition, we show the microbump assignment methodology to handle a large number of 3-D interconnections in the microbumping 3-D design. We also perform SI on the new set of 3-D intertier/interdie connections to discuss the reliability based on their physical dimensions. With a new benchmark design, the hybrid-bonding 3-D shows the best energy–delay-product (EDP) improvement, which is 25.8% compared to 2-D, and the largest eye-opening among 3-D integration options.