Minor-embedding heuristics for large-scale annealing processors with sparse hardware graphs of up to 102,400 nodes
Yuya Sugie, Yuki Yoshida, Normann Mertig, Takashi Takemoto, Hiroshi Teramoto, Atsuyoshi Nakamura, Ichigaku Takigawa, Shin-ichi Minato, Masanao Yamaoka, Tamiki Komatsuzaki
Topics & Concepts
EmbeddingHeuristicsComputer scienceSimulated annealingParallel computingDiscrete mathematicsTheoretical computer scienceMathematicsAlgorithmMathematical optimizationArtificial intelligenceQuantum Computing Algorithms and ArchitectureComplexity and Algorithms in GraphsStochastic Gradient Optimization Techniques