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A 0.90-Tb/s/in 1.29-pJ/b Wireline Transceiver With Single-Ended Crosstalk Cancellation Coding Scheme for High-Density Interconnects

Qian Liu, Li Du, Yuan Du

2023IEEE Journal of Solid-State Circuits28 citationsDOI

Abstract

This article presents a four-lane single-ended transceiver featuring a crosstalk-canceling coding scheme, Fibonacci coding (FC), which supports high-speed transmission over high-density parallel inter-chip channels. In-depth experiments and analyses are presented to evaluate FC’s performance, and the results suggest that the FC scheme can provide significant near-end and far-end crosstalk cancellation (XTC) while maintaining high channel density for high-speed multi-lane inter-chip links. By simulation, an effective data rate of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4\times8.5$ </tex-math></inline-formula> Gb/s is enhanced to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3\times18$ </tex-math></inline-formula> Gb/s by FC for a four-channel link. The transceiver, including an FC codec, a feed-forward equalizer (FFE), and a continuous-time linear equalizer (CTLE), is implemented in 28-nm CMOS. It achieves a data rate density of 0.90 Tb/s/in with an energy efficiency of 1.29 pJ/b and an area of 0.004 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /lane. The performance of FC is measured on 3.8-mil-spaced four-lane coupled printed circuit board (PCB) microstrips. For the 2-in wires, the peak-to-peak jitter of the received eye is reduced by 45.0% at 10 Gb/s, and the horizontal aperture is broadened to 0.58 UI at a bit error rate (BER) <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$&lt; 10^{-12}$ </tex-math></inline-formula> by activating the FC scheme and equalizers. For the 5-in wires, the jitter is reduced by 43.9% and the eye is 0.47-UI-wide at 8.5 Gb/s. And for the 8-in wires, the jitter is reduced by 49.0% and the eye is 0.43-UI-wide at 6 Gb/s.

Topics & Concepts

TransceiverCMOSCoding (social sciences)ChipComputer scienceElectronic engineeringComputer hardwareTopology (electrical circuits)Electrical engineeringMathematicsTelecommunicationsEngineeringStatisticsInterconnection Networks and SystemsAdvancements in PLL and VCO TechnologiesLow-power high-performance VLSI design
A 0.90-Tb/s/in 1.29-pJ/b Wireline Transceiver With Single-Ended Crosstalk Cancellation Coding Scheme for High-Density Interconnects | Litcius