Breakdown voltage capability of vertical 4H–SiC power devices
Philippe Godignon, J. Biscarrat, Miya Tranchesset, Romain Laviéville, Dominique Tournier, Pierre Brosselard, J. Montserrat
Abstract
Power semiconductor devices are constructed to endure high voltages (>30 V) and manage high current density. Edge termination is a specific feature that must be integrated into the device architecture to achieve high voltage capability in vertical power components. It is necessary to design these edge terminations while taking into account the device's architecture and technology. Termination efficiency is the main factor, but its area is also of great significance. Many edge termination designs with efficiency close to 100 % have been reported and are currently used in commercial devices. However, having a near-100 % static breakdown voltage is not the only requirement in modern power devices. Today, most power applications rely on the avalanche capability as a key parameter. Avalanche capability is defined by the device ability to enter in non-destructive avalanche mode, where the component can temporarily sustain a high voltage and a high current in blocking mode. The Unclamped Inductive Switching (UIS) test can be used to measure the avalanche mode, and it can be customized to define a safe operating area for a full avalanche mode (SOA). The safe operation of both single pulse and repetitive pulsed avalanche limits can be characterized. Such operation mode is now controlled in both Silicon and Silicon Carbide based power devices. However, the development of novel wide and ultra-wide band gap semiconductors in regards to avalanche capability and SOA still require a lot of work.