Capacitor-Less 4F DRAM Using Vertical InGaAs Junction for Ultimate Cell Scalability<sup/>
Joon Pyo Kim, Jaeho Sim, Pavlo Bidenko, Dae‐Myeong Geum, Seong Kwang Kim, Joonsup Shim, Jongmin Kim, Sanghyeon Kim
Abstract
In this work, we demonstrated capacitor-less 4F2 2-terminal InGaAs npn junction DRAM through careful device design. Using epitaxially grown InGaAs which have a steep junction, fabricated InGaAs bistable resistor (biristor) DRAM showed low voltage operation (~2 V), fast switching speed (<20 ns), long-term retention (103 s at 85 °C), and high endurance (>1010 cycles) with a high sensing margin. Considering this feasibility study, we believe that InGaAs <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{n}^{+}$ </tex-math></inline-formula> pn+ junction DRAM could be a good technological option for future scalable 3D DRAM.