Litcius/Paper detail

Improving 3-D NAND SSD Read Performance by Parallelizing Read-Retry

Jinhua Cui, Zhimin Zeng, Jianhang Huang, Weiqi Yuan, Laurence T. Yang

2022IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems14 citationsDOI

Abstract

With the bit density improvement and the 3-D flash techniques, modern NAND flash-memory-based solid-state disks (SSDs) dramatically increase the flash storage capacity. However, in high-density SSDs, the long read latency overheads due to massive read-retry steps have become a serious performance concern to develop flash memory in storage devices. In this article, we proposed a parallel read-retry scheme (PaRR) to utilize the read-retry characteristics among flash memory cells. Specifically, when reading the multiple data pages simultaneously, PaRR reduces the read-response time by parallelizing read-retry operations. PaRR reduces the number of read-retry operations by parallelizing read-retry steps with the different aggressive read reference voltages if simultaneously reading the data pages that exhibit virtually equivalent reliability characteristic. Our evaluation shows that PaRR improves the I/O performance by 33.77% on average compared with the state-of-the-art scheme.

Topics & Concepts

Computer scienceFlash (photography)NAND gateFlash memoryReading (process)Latency (audio)Flash file systemComputer hardwareParallel computingEmbedded systemOperating systemComputer memoryLogic gateSemiconductor memoryAlgorithmTelecommunicationsPolitical scienceArtVisual artsLawAdvanced Data Storage TechnologiesCaching and Content DeliveryCellular Automata and Applications