A Novel Gate-Controlled Dual Direction SCR With Enhanced Failure Current for On-Chip ESD Protection of Industry-Level Controller Area Network Bus
Yang Wang, Zeyu Zhong, Xiangliang Jin, Yan Peng, Jun Luo, Jun Yang
Abstract
The working environment of the industry-level high-voltage communication bus is harsh. Strong electrostatic interference has become one of the key factors affecting the stability of the core module. However, the traditional silicon-controlled rectifier (SCR) is difficult to meet the electrostatic discharge (ESD) design requirements for high-voltage applications. Therefore, this article proposes a novel enhanced gate-controlled dual-direction SCR (EGC-DDSCR) with a high failure current, which can effectively ensure the ESD reliability of the controller area network (CAN) bus. By comparing the ESD performance of EGC-DDSCR, traditional gate-controlled DDSCR (GC-DDSCR), and double-GC-DDSCR (DGC-DDSCR), the physical behavior of the gate control mechanism is explored. Three types of SCR are designed based on a 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> BCD process. According to the physical principles of devices, 2-D electrical simulation and transmission line pulse (TLP) test results predict and verify the ESD parameters of the SCRs. The results show that EGC-DDSCR ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.64~\Omega$ </tex-math></inline-formula> ) has a smaller ON-resistance ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$R_{\mathrm{\scriptscriptstyle ON}}$ </tex-math></inline-formula> ) and higher robustness than GC-DDSCR ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.98~\Omega$ </tex-math></inline-formula> ) and DGC-DDSCR ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.90~\Omega$ </tex-math></inline-formula> ). In addition, the trigger voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{t1}$ </tex-math></inline-formula> :42.7 V), holding voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{h}$ </tex-math></inline-formula> :31.0 V), and failure current ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I_{t2}$ </tex-math></inline-formula> :16.7 A) of the device fully meet the ESD window of the target chip. EGC-DDSCR can be stably applied to CANL and CANH interfaces for on- chip bidirectional ESD protection.