Litcius/Paper detail

Study of Cryogenic MOSFET Sub-Threshold Swing Using <i>Ab Initio</i> Calculation

Tom Jiao, Edwin Antunez, Hiu Yung Wong

2023IEEE Electron Device Letters10 citationsDOI

Abstract

The abnormal subthreshold swing (SS) in Silicon Metal-Oxide Semiconductor Field Effect Transistor (MOSFET) at cryogenic temperature is commonly attributed to band tail (BT) conduction. The cryogenic SS does not scale with the temperature, T, for T <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$ &lt; 50\text{K}$ </tex-math></inline-formula> and it is observed to saturate at 10mV/dec ~ 20mV/dec at low T in most experiments. Hitherto, only analytical studies have been conducted for BT and its properties. It is not clear how much of its effect can be eliminated should there be an ideal manufacturing technology. In this letter, by using robust ab initio calculation with quantum transport, we have successfully calculated the BT in a Si nanowire (NW) and studied its characteristic length. By analyzing the transport properties of the NW with various gate lengths, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{L}_{{\text {G}}}$ </tex-math></inline-formula> , at various temperatures, it is observed that for <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{L}_{{\text {G}}} &lt; 20$ </tex-math></inline-formula> nm, the tunneling current dominates, and for <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{L}_{{\text {G}}}&gt;$ </tex-math></inline-formula> 20nm, the BT current dominates at 3K. It is found that, in a perfect nanowire (as a gedanken experimental device), an SS as low as 1.4mV/dec can be achieved at 3K for 15 orders of magnitudes of current change with a minimum of 0.42mV/dec ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{L}_{{\text {G}}}$ </tex-math></inline-formula> = 50nm). This also justifies the results in a recent experiment in which a very low SS (3.4mV/dec at 5.5K) was obtained. Moreover, it is also shown that for the 2nm node ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{L}_{{\text {G}}}~\sim $ </tex-math></inline-formula> 15nm), direct S/D tunneling will set the ultimate limit of SS at 3K.

Topics & Concepts

Ab initioQuantum tunnellingMOSFETPhysicsElectrical engineeringMaterials scienceTopology (electrical circuits)Condensed matter physicsTransistorQuantum mechanicsMathematicsCombinatoricsEngineeringVoltageSemiconductor materials and devicesAdvancements in Semiconductor Devices and Circuit DesignSemiconductor materials and interfaces