A 192-Gb 12-High 896-GB/s HBM3 DRAM With a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization
Myeong-Jae Park, Jinhyung Lee, Kyungjun Cho, Jihwan Park, Junil Moon, Sung-Hak Lee, Tae‐Kyun Kim, Sanghoon Oh, Seok-Woo Choi, Yongsuk Choi, Ho Sung Cho, Tae-Sik Yun, Young Jun Koo, Jae‐Seung Lee, Byung-Kuk Yoon, Young‐Jun Park, Sangmuk Oh, Chang Kwon Lee, Seong-Hee Lee, Hyun-Woo Kim, Yucheon Ju, Seung-Kyun Lim, Kyo Yun Lee, Sang-Hoon Lee, Woo Sung We, Seungchan Kim, Seung Min Yang, Keonho Lee, In-Keun Kim, Younghyun Jeon, Jae Hyung Park, Jong Chan Yun, Seonyeol Kim, Dong-Yeol Lee, Su-Hyun Oh, Junghyun Shin, Yeonho Lee, Jieun Jang, Joohwan Cho
Abstract
This article introduces a 192-Gb 896-GB/s 12-high stacked third-generation high-bandwidth memory (HBM3 DRAM) with low power consumption and high-reliability traits. New design schemes and features, including internal low-voltage signaling, center strobe calibration, through-silicon via (TSV) auto-calibration, a symbol-correcting in-DRAM ECC, and machine-learning-based layout optimization, allow large amounts of data transfers among the vertically stacked base and core dies with limited delay mismatch or SI degradation, as well as reduced power consumption from low-voltage swings. Experimental results confirm 896-GB/s bandwidth operations at 1.0-V voltage conditions with up to 15% improved power efficiency.