A Supply Voltage Noise Immunity Enhancement Design for High-Voltage Gate Driver IC Based on Bootstrap Circuit
Woo-Kang Jin, Kunhee Cho
Abstract
One important design aspect of a high-voltage gate driver integrated circuit (HVIC) is safety because the failure operation such as latch-on failure may cause severe damage to the system and may pose physical harm to the user. In the HVIC, a noise on the high-side supply voltage was considered as the main source of failure operation, however, a low-side supply voltage noise also can cause latch-on failure to the high-side circuitry. In this brief, the failure caused by the high-side as well as low-side supply voltage noise is analyzed, and a supply voltage noise immunity enhancement design for HVIC is described. The HVIC has been implemented in a 1.2 μm 600 V BCDMOS process. The proposed design shows a latch-on free operation from the various slope of the supply voltage drops while the conventional design shows shoot-through failure by latch-on failure. The approach is well suited for the harsh supply voltage environment such as the automotive application.