Fully Self-Aligned Via Integration for Interconnect Scaling Beyond 3nm Node
H.P. Chen, Yiliang Wu, Huai Huang, Ching‐Hui Tsai, S.K. Lee, Chang‐Chun Lee, Tzu-Hsiang Wei, Huizhen Yao, Y.C. Wang, Chan-Yu Liao, Hsiaokang Chang, C.W. Lu, W.S. Shue, Min Cao
Abstract
Two fully self-aligned via (SAV) integration schemes by metal recess approach and area-selective dielectric-on-dielectric (DoD) method are reported in this paper. A topography with enlarged diagonal distance is essential for the vias to be self-aligned. The metal recess approach encounters challenge of poor uniformity, high surface roughness, and degraded metal integrity. The DoD approach featuring an upward dielectric terrace deposited by selective-SAM-blocking method shows two orders of magnitude improvement in via-to-line time dependent dielectric breakdown (TDDB). Furthermore, this work demonstrates that high selectivity DoD can achieve industry standards of via and line resistance performance, via-chain functional yield, and metal line TDDB and electromigration (EM) reliability. In summary, the SAV by DoD is a viable approach to enable interconnect scaling beyond 3nm node.