Miniaturized 3D Functional Interposer Using Bumpless Chip-on-Wafer (COW) Integration with Capacitors
Tatsuya FUNAKI, Yoshiaki Satake, Kyosuke Kobinata, Chih-Cheng Hsiao, Hitoshi Matsuno, Shunsuke Abe, Young-Suk Kim, Takayuki Ohba
Abstract
Chip-on-Wafer (COW) integration technology characterized by bumpless Cu interconnects between Si capacitor and re-distribution layer (RDL) was achieved for the first time. For fabricating a functional interposer using 300 mm Si wafer, a capacitor was embedded in a Si interposer with a thin layer of adhesive and mold resin. The bumpless Cu interconnects were realized with through silicon vias (TSVs), which are vertical interconnects between the upper and lower layer to shorten the interconnect length between the Si capacitor and the RDL. This 3D functional interposer enables significant reduction in the package area (down to 1/2) and the interconnect length (below 1/100).