A High-Performance and Secure TRNG Based on Chaotic Cellular Automata Topology
Yukui Luo, Wenhao Wang, Scott Best, Yanzhi Wang, Xiaolin Xu
Abstract
As an important hardware security primitive, the true random number generator (TRNG) has been widely utilized in many critical applications. The performance and security of TRNGs are always dominant features that determine the usability of a TRNG scheme. In this article, we propose a novel TRNG design method based on a self-timed ring structure. Different from most existing self-timed circuit-based TRNGs that use ring oscillators, the basic circuit component of the proposed TRNG is a digital realization of a chaotic cellular automata topology. We utilize three different methods to validate the proposed TRNG method, including HSpice simulation, FPGA prototype, and ASIC test chips. As the proposed TRNG structure is pure digital, thus it is synthesizable with standard all-digital components. The test chips of the proposed TRNG structure are fabricated with 40 nm TSMC technology node, with a hardware footprint equals to 75 NAND gates and a die area of 270 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . With a PCIe setup connecting the testchip and computer, the TRNGs achieves high throughput as 1600 Mb/s. The FPGA implementation is built on a Virtex6 family FPGA from Xilinx, which also achieves lightweight overhead: 53 look-up-table (LUT) and 22 D Flip-flops (DFF). The collected random numbers from FPGA implementations and ASIC testchips are comprehensively tested with three test suites, including NIST SP800-22, NIST SP800-90B, and AIS-31 with a high pass-rate. Further, the security of the TRNG testchips and FPGA implementations are validated by applying three different attacks, including frequency injection attacks, power attacks, and thermal attacks. The experimental results demonstrate that the proposed TRNG structure is immune to these attacks with trivial entropy loss.