Design and Characterization of n/p-well CMOS SPAD With Low Dark Count Rate and High Photon Detection Efficiency
Jau-Yang Wu, Chun-Hsien Liu
Abstract
We have proposed a structure design of single-photon avalanche diode fabricated in the Taiwan Semiconductor Manufacturing Company Ltd. (TSMC) 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> high-voltage (HV) CMOS technology, which improves the limited operating excess voltage for an n-on-p design without any other customized well layer. With the introduction of a deep p-well isolation (ISO) layer, the excess bias is significantly elevated, so that the device exhibits high photon detection probability (PDP) with relatively low dark count rate. The n-on-p-type device is favorable for 3-D-stacked backside illuminated structure and can attain high PDP at longer wavelength. With the improved jitter and after-pulsing probability, our designed device can be suitable for the application of light detection and ranging (LiDAR).