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Memory Array Demonstration of fully integrated 1T-1C FeFET concept with separated ferroelectric MFM device in interconnect layer

Konrad Seidel, David Lehninger, Raik Hoffmann, Tarek Ali, Maximilian Lederer, Ricardo Revello, Konstantin Mertens, Kati Biedermann, Yukai Shen, Defu Wang, Matthias Landwehr, Andreas Heinig, Thomas Kämpfe, Hannes Mähne, Kerstin Bernert, Steffen Thiem

20222022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)21 citationsDOI

Abstract

In our work we describe and demonstrate an alternative approach of integrating 1T-1C FeFET having separated transistor (1T) without modifying frontend CMOS technology and an additional gate-coupled ferroelectric (FE) capacitor (1C) embedded in the interconnect layers. Starting from the results of FE capacitor integration and 1T-1C single cell characterization this paper describes realization and results of a fully integrated 8 kbit memory array implementation.

Topics & Concepts

InterconnectionCapacitorRealization (probability)Ferroelectric capacitorFerroelectricityMaterials scienceOptoelectronicsTransistorNon-volatile memoryCMOSMemory cellElectrical engineeringElectronic engineeringLayer (electronics)Computer scienceEngineeringNanotechnologyTelecommunicationsVoltageMathematicsStatisticsDielectricFerroelectric and Negative Capacitance DevicesSemiconductor materials and devicesAdvanced Memory and Neural Computing
Memory Array Demonstration of fully integrated 1T-1C FeFET concept with separated ferroelectric MFM device in interconnect layer | Litcius