Low-area and high-speed hardware architectures of LBlock cipher for Internet of Things image encryption
Pulkit Singh, Bibhudendra Acharya, Rahul Kumar Chaurasiya
Abstract
Security is becoming an essential field of research as network technology is changing at a rapid pace. Digital images are transmitted in many modes of communication. This transmission must be secure, particularly in applications that demand a high level of security, such as military applications, surveillance, radars, and biometrics. Two hardware solutions of the lightweight block cipher LBlock are provided to secure image data. These proposed architectures are implemented on a Xilinx field programmable gate arrays (FPGA) platform, and the implementation results are compared with existing state-of-the-art designs. The proposed designs took 56 and 64 slices operating at a frequency of 492.441 and 681.663 MHz, respectively, on a Virtex-5 FPGA platform. In addition, the proposed round-based and pipelined designs showed improvement in hardware efficiency over state-of-the-art designs. The proposed hardware architectures are capable of securing different sizes of gray-scale and RGB color images. These hardware solutions were verified by different analyses, including correlation coefficient, mean square error (MSE), peak signal-to-noise ratio (PSNR), histogram, entropy, number of pixel changing rate (NPCR), and unified average changing intensity (UACI). The existing solutions were compared with correlation coefficients, NPCR, UACI, MSE, PSNR, and entropy values and provide better solutions than the state-of-the-art designs.