A 26-32GHz Differential Attenuator with 0.23dB RMS Attenuation Error and 11.2dBm IP1dB in 40nm CMOS Process
An Sun, Junjie Gu, Hao Xu, Weitian Liu, Kefeng Han, Rui Yin, Zongming Duan, Hao Gao, Na Yan
Abstract
This paper presents a 26-32GHz 6-bit differential attenuator in 40nm CMOS process. This attenuator adopts an optimized cascade scheme that incorporates simplified T-type (ST-type), T-type and Π-type attenuator units. Driven by a complete analysis of the pole-zero pattern introduced by the compensation capacitor, the design achieves a state-of-art uncalibrated RMS attenuation and phase error. The design methodology of shunt branches for constant phase and cascade linearity enhancement achieves a high linearity while minimizing the phase variation across the whole frequency band. The attenuator achieves a 31.5dB attenuation range with 0.5dB step and -8.5 to -9.5dB insertion loss in a compact area of 0.54mm×0.23mm. The measured RMS attenuation error remains below 0.23dB without calibration and phase error is less than 5.58◦. IP1dB in the reference state is better than 11.2dBm across 26–32GHz.