RISC32-LP: Low-Power FPGA-Based IoT Sensor Nodes With Energy Reduction Program Analyzer
Beng-Liong Tan, Kai‐Ming Mok, Jing-Jing Chang, Wai‐Kong Lee, Seong Oun Hwang
Abstract
Field-programmable gate array (FPGA)-based sensor nodes are popular for their flexible design approach and field reconfigurability. RISC32 is one of the recent Internet of Things (IoT) processors proposed for the development of FPGA-based sensor nodes, and it includes the ability to reconfigure the microarchitecture on the fly in order to reduce dynamic energy consumption. However, such a method does not minimize static energy consumption, which is important in FPGA-based systems. In this work, clock gating (CG) and dynamic voltage and frequency scaling (DVFS) are applied to further reduce the energy consumption in RISC32. In the research presented here, we implemented a new software called the energy reduction program analyzer to estimate the parameters that configure a sensor node to achieve minimum energy consumption, targeting the typical IoT application scenario. Experimental results show that the low-power techniques applied in this work (RISC32-LP) can reduce energy consumption by 47%, compared to the standard RISC32 processor.