Two Stage CTLE For High Speed Data Receiving
Grigoryan T. Manvel, Atanesyan A. Arman, Hakobyan H. Garik, Harutyunyan S. Sergo
Abstract
It has been designed continuous time linear equalizer (CTLE) for high frequency data receiving based on neg-C technique implementation. CTLE design have two blocks: conventional diff pair with source degeneration capacitance and resistance and negative capacitance connected to the output of CTLE which is giving opportunity to control CTLE AC performance. Also, neg-C has configuration option which is making possible to have wide operating frequency range, in practice range from 2GHz to 5GHz. CTLE poles and zeros mostly depends on diff pair degeneration capacitance and resistance also, added neg-C impedance to diff pair output. Neg-C parameters configuration is given by current DAC, so neg-C current is simply controlled by digital code. Advantage of circuit is controllability and high operating frequency, and it can be used in such Ser-Des protocols like USB (Universal serial bus) and PCIe (Peripheral component interconnect express). Implementation of neg-C circuit slight inserts variation of DC gain and it can be considered as a disadvantage of proposed circuit.