A trigonometric hardware acceleration in 32-bit RISC-V microcontroller with custom instruction
Khai-Duy Nguyen, Dang Tuan Kiet, Trong-Thuc Hoang, Nguyen Quang Nhu Quynh, Xuan‐Tu Tran, Cong‐Kha Pham
Abstract
This work presents a 32-bit Reduced Instruction Set Computer fifth-generation (RISC-V) microprocessor with a COordinate Rotation DIgital Computer (CORDIC) accelerator. The accelerator is implemented inside the core and being used by the software via custom instruction. The used microprocessor is the VexRiscv with the Instruction Set Architecture (ISA) of RV32IM; that means 32-bit RISC-V including Integer and Multiplication. The experimental results were collected using Field-Programmable Gate Array (FPGA) on the DE2-115 development kit and Application Specific Integrated Chip (ASIC) synthesizer on 180-nm CMOS process library.
Topics & Concepts
Reduced instruction set computingComputer scienceInstruction setMicroprocessorField-programmable gate arrayApplication-specific integrated circuitComputer hardwareMicrocontrollerCORDIC16-bitEmbedded system32-bitHardware accelerationSoftwareOperating systemNumerical Methods and AlgorithmsAdvancements in PLL and VCO TechnologiesLow-power high-performance VLSI design