IP Core Steganography Using Switch Based Key-Driven Hash-Chaining and Encoding for Securing DSP Kernels Used in CE Systems
Mahendra Rathor, Anirban Sengupta
Abstract
Intellectual property (IP) core of digital signal processing (DSP) kernels act as hardware accelerators in consumer electronics (CE) systems. However due to rising threats of cloning and counterfeiting to an IP core, security remains an important subject of research for these hardware accelerators. This paper presents a novel key-driven hash-chaining based hardware steganography for securing such IP cores used in CE systems. The proposed approach is capable to implant secret invisible stego-marks in design using hash-chaining process that incorporates switches, strong large stego-keys, multiple encoding algorithms and hash blocks. The methodology proposed provides massive security against IP cloning and counterfeiting while incurring nominal design overhead (<; 0.3 %). The results of the proposed approach on comparison with state of the art indicated significantly stronger digital evidence (lower probability of co-incidence), stronger key size (in bits) and lower design cost using proposed stego-marks. Further, from an attacker's perspective, the proposed steganography increases an attacker's effort manifold during decoding the valid stego-key value (for generating/extracting original secret stego-mark), compared to existing approaches.