Victima: Drastically Increasing Address Translation Reach by Leveraging Underutilized Cache Resources
Konstantinos Kanellopoulos, Hong Chul Nam, Nisa Bostanci, Rahul Bera, Mohammad Sadrosadati, Rakesh Kumar, Davide B. Bartolini, Onur Mutlu
Abstract
Address translation is a performance bottleneck in data-intensive workloads due to large datasets and irregular access patterns that lead to frequent high-latency page table walks (PTWs). PTWs can be reduced by using (i) large hardware TLBs or (ii) large software-managed TLBs. Unfortunately, both solutions have significant drawbacks: increased access latency, power and area (for hardware TLBs), and costly memory accesses, the need for large contiguous memory blocks, and complex OS modifications (for software-managed TLBs).
Topics & Concepts
Computer scienceBottleneckLatency (audio)CacheSoftwareParallel computingOperating systemEmbedded systemAccess timeData accessTranslation lookaside bufferTable (database)Physical addressDatabaseSemiconductor memoryTelecommunicationsAdvanced Data Storage TechnologiesParallel Computing and Optimization TechniquesCloud Computing and Resource Management