Verification methods for complex-functional blocks in CAD for chips deep submicron design standards
Vladimir Zolnikov, Konstantin Zolnikov, Nadezhda Ilina, Kirill Grabovy
Abstract
The article discusses the design stages of very large-scale integrated circuits (VLSI) and the features of the procedure for verifying complex-functional VLSI blocks. The main approaches to microcircuit verification procedures are analyzed to minimize the duration of verification cycles. In practice, a combination of several approaches to verification is usually used.
Topics & Concepts
Very-large-scale integrationComputer scienceFunctional verificationComputer architectureCADComputer engineeringReliability engineeringElectronic engineeringEmbedded systemFormal verificationEngineering drawingProgramming languageEngineeringAerospace, Electronics, Mathematical ModelingAdvanced Theoretical and Applied Studies in Material Sciences and GeometryEngineering Technology and Methodologies