Analysis of the Role of Interfacial Layer in Ferroelectric FET Failure as a Memory Cell
S. Lee, Haesung Kim, Hyojin Yang, Sanghyuk Yun, Junseong Park, Haneul Lee, Sejun Park, Sung‐Jin Choi, Dae Hwan Kim, Dong Myong Kim, Daewoong Kwon, Jong‐Ho Bae
Abstract
By observing temporary and permanent changes in threshold voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {T}}$ </tex-math></inline-formula> ) due to the application of unipolar/bipolar stress, it was confirmed that the trap-carrier interaction speed is the cause of failure of the ferroelectric transistor as a memory. As the polarization switching occurs, carriers are trapped in the ferroelectric/interfacial layer (FE/IL), and the hole trap is limited compared to the electron trap due to the slow interaction. IL degrades under bipolar stress due to the high electric field during polarization switching, leading to the acceleration of hole trapping, which has a strong impact on the memory window.