Quantum circuit optimizations for NISQ architectures
Beatrice Nash, Vlad Gheorghiu, Michele Mosca
Abstract
Abstract Currently available quantum computing hardware platforms have limited 2-qubit connectivity among their addressable qubits. In order to run a generic quantum algorithm on such a platform, one has to transform the initial logical quantum circuit describing the algorithm into an equivalent one that obeys the connectivity restrictions. In this work we construct a circuit synthesis scheme that takes as input the qubit connectivity graph and a quantum circuit over the gate set generated by <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML" overflow="scroll"> <mml:mo stretchy="false">{</mml:mo> <mml:mi>CNOT</mml:mi> <mml:mo>,</mml:mo> <mml:msub> <mml:mrow> <mml:mi>R</mml:mi> </mml:mrow> <mml:mrow> <mml:mi>Z</mml:mi> </mml:mrow> </mml:msub> <mml:mo stretchy="false">}</mml:mo> </mml:math> and outputs a circuit that respects the connectivity of the device. As a concrete application, we apply our techniques to Google’s Bristlecone 72-qubit quantum chip connectivity, IBM’s Tokyo 20-qubit quantum chip connectivity, and Rigetti’s Acorn 19-qubit quantum chip connectivity. In addition, we also compare the performance of our scheme as a function of sparseness of randomly generated quantum circuits, and discuss how to apply our techniques as a subroutine for the more general mapping problem over universal set of gates (Clifford + T).