A 2.87μW 1kHz-BW 94.0dB-SNDR 2-0 MASH ADC Using FIA with Dynamic-Body-Biasing Assisted CLS Technique
Yaopeng Hu, Yibo Zhao, Wanyuan Qu, Le Ye, Menglian Zhao, Zhichao Tan
Abstract
Micro-power ΔΣ modulators are suitable for low-bandwidth, high-precision applications, such as smart sensors, biomedical signal processing and battery-powered IoT devices. They achieve high SNR by oversampling and noise shaping, but higher order loops have stability problems. The multistage noise-shaping (MASH) technique solves this problem by realizing a high-order NTF with several low-order stages. However, for the MASH structure to be effective, the loop filter integrators must have high gain to avoid quantization noise leakage. Conventionally, they are realized by high-gain OTAs with gain-boosted cascode [1].However, they draw static bias current, and their biasing and common mode feedback (CMFB) make them unattractive in duty-cycled operation in IoT applications due to the long settling time. The floating-inverter amplifier (FIA) [2] does not require biasing and CMFB, which makes it an attractive option for IoT applications. However, cascade topologies are needed to achieve high gain in [2–3], which increases complexity and area since each stage contributes a pole and requires a reservoir capacitor (C <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RES</inf> ). An additional C <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RES</inf> is used in the output stage of [3] to optimize the settling performance and stability, which costs further area. This paper presents a dynamic-body-biasing assisted correlated level shifting (CLS) technique to boost the DC gain of a single-stage FIA with only one reservoir capacitor to above 66dB with minimal area overhead. This enables a fully dynamic MASH ADC that consumes 2.87μW while achieving 96.9dB DR and 94.0dB SNDR in 1kHz BW at an OSR of 125×, resulting in a SNDR-based Schreier FoM of 179.4dB.