Gate Oxide Thickness and Drain Current Variation of Dual Gate Tunnel Field Effect Transistor
S. Howldar, B. Balaji, K. Srinivasa Rao
Abstract
Two-dimensional analytical modelling of Dual Material Gate Tunnel Field Effect Transistor with change in variation of gate oxide thickness (DMG-UOX-TFET) is proposed in this work. This proposed device employs dielectric materials such as hafnium oxide and silicon dioxide, with distinct oxide thicknesses. This device was invented using a technology-aided computer design tool in 10 nm (0.01 µm) technology. This work investigates the impact of gate oxide thickness on the electrical characteristics of the proposed device, with a particular focus on drain current variation. The extensive simulations and key performance parameters of the proposed device were analyzed regarding gate oxide thickness. The various gate oxide thicknesses and their effects on the device subthreshold slope, On- current, Off- current, and on-off-current ratio were analyzed. The proposed device incorporates n-type operations within the gate overlap region, effectively mitigating the corner effect and the detrimental band-to-band tunneling that can degrade the on/off ratio. Through careful optimization of the doping concentration in the gate overlap region, achieved a remarkable ∼4.8 time enhancement in the on-current, while simultaneously reducing the average subthreshold swing from 91.3 mV/dec to 52.8 mV/dec.