A 2.0-to-7.4-GHz 16-Phase Delay-Locked Loop With a Sub-0.6-ps Phase-Delay Error in 40-nm CMOS
Jian Yang, Quan Pan, Jun Yin, Pui‐In Mak
Abstract
This article reports a 2.0-to-7.4-GHz 16-phase single-loop delay-locked loop (DLL) with high phase accuracy and wide locking range. It features a cascode current splitting charge pump (CP) to effectively suppress the current mismatch and the phase-delay error among the 16-phase outputs. Also, the proposed lock detector (LD) resolves the false-and harmonic-locking issues, extending the detection range from 3 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$T_{\mathrm{REF}}$</tex-math> </inline-formula> /2 to 8 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$T_{\mathrm{REF}}$</tex-math> </inline-formula> /3. Fabricated in 40-nm CMOS, the prototyped DLL achieves low phase-delay errors of 0.50 ps (0.36 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{\circ})$</tex-math> </inline-formula> at 2.0 GHz and 0.58 ps (1.55 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{\circ})$</tex-math> </inline-formula> at 7.4 GHz, respectively. The DLL occupies a compact area of 0.0168 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{2}$</tex-math> </inline-formula> and consumes 18.3 mW at 7.4 GHz under a 1.1-V supply; the result corresponds to a power efficiency of 0.15 mW/GHz/phase that compares favorably with the state of the art.