3D V-Cache: the Implementation of a Hybrid-Bonded 64MB Stacked Cache for a 7nm x86-64 CPU
John Wuu, Rahul Agarwal, Michael Ciraula, Carl Dietz, Brett C. Johnson, Dave Johnson, Russell Schreiber, Raja Swaminathan, W. Laurens Walker, Samuel Naffziger
Abstract
AMD's V-Cache is a 3D stacked product that attaches additional cache onto a high-performance processor through hybrid bonding, a technology that offers significant bandwidth and power benefits over state-of-the-art uBump based approaches. V-Cache expands Zen3's on-die L3 Cache from 32MB to 96MB, providing up to 2TB/s of bandwidth and 15% average gaming performance uplift. This paper describes the hybrid bonding technology components, provides insight into the V-Cache's architecture and design, discusses the associated DFT implications, and offers measured performance results.
Topics & Concepts
CacheComputer scienceCache pollutionSmart CacheCache algorithmsCache coloringx86Cache invalidationPage cacheParallel computingBandwidth (computing)Computer architectureEmbedded systemCPU cacheOperating systemComputer networkSoftwareParallel Computing and Optimization TechniquesInterconnection Networks and SystemsEmbedded Systems Design Techniques