A Methodology for Simulating Multi-chiplet Systems Using Open-source Simulators
Haocong Zhi, Xianuo Xu, Weijian Han, Zhilin Gao, Xiaohang Wang, Maurizio Palesi, Amit Kumar Singh, Letian Huang
Abstract
Multi-chiplet systems are a new design paradigm to mitigate the chip design cost and improve yield for complex SoCs. The design space of multi-chiplet systems is much larger compared to a single chip SoC system. To support early stage design space exploration, simulators are of paramount importance. However, existing open-source multi-/many-core simulators are not suitable for simulating large-scale multi-chiplet systems due to the following reasons: 1) lack of accurate inter-chiplet interconnection model, and 2) incapable of supporting large-scale parallel simulation with accurate interconnection modelling. Therefore, we propose a methodology for building up a simulator for multi-chiplet systems using open-source simulators like gem5, sniper, gpgpu-sim, etc. This simulation methodology mimics the reuse and integration idea of chiplets, that is, these existing open-source simulators are reused to simulate individual chiplets, and an inter-simulator-process communication and synchronization protocol is proposed to simulate inter-chiplet communication. The proposed simulation methodology has the following features: 1) Parallel simulation for large-scale systems is supported with inter- and intra-chiplet interconnection accurately modelled. 2) Both distributed and shared memory models are supported for multi-chiplet systems. We also provide a method to modify the code of the open-source simulators like gem5, sniper, gpgpu-sim, etc. for multi-chiplet simulation, and we have released the source code of multi-chiplet simulators based on gem5, sniper, gpgpu-sim at https://github.com/FCAS-SCUT/chiplet_simulators. In the future we will port more applications/benchmarks and integrate more open-source simulators.