Design of a nonvolatile-register-embedded RISC-V CPU with software-controlled data-retention and hardware-acceleration functions
Masanori Natsui, Keisuke Sakamoto, Takahiro Hanyu
Abstract
This paper describes the design of a nonvolatile CPU based on RISC-V that is an open-source and highly flexible instruction set architecture. This CPU incorporates nonvolatile registers utilizing magnetic tunnel junction (MTJ) device, as well as custom instructions specific to the control of these nonvolatile registers and an accelerator module embedded into the CPU architecture. These techniques enable efficient execution of intermittent operations suitable for energy-limited internet-of-things (IoT) applications. Through performance evaluation of the CPU designed in a 55-nm CMOS/MTJ-hybrid process technology, we show that our CPU can save up to 56.9% of power consumption compared to conventional ones, with an average power consumption of 3.91 μW/MHz.