A 900-MS/s SAR-Based Time-Interleaved ADC With a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations
Gabriele Bè, Angelo Parisi, Luca Bertulessi, Luca Ricci, Lorenzo Scaletti, Mario Mercandelli, Andrea L. Lacaita, Salvatore Levantino, Carlo Samori, Andrea Bonfanti
Abstract
This brief presents a 12-bit successive approximation register (SAR)-based time-interleaved (TI) analog-to-digital converter (ADC) with a fully programmable interleaving factor. A total of six SAR sub-ADCs can be time-interleaved. The interleaving factor is programmable from 2 to 6, resulting in an overall sampling rate from 300 to 900MS/s. On-chip offset, gain, and timing skew background calibrations allow reducing the interleaving spurs to less than −73dBc in every configuration. In particular, the proposed difference-based skew calibration efficiently operates in any configuration, not being limited to power-of-2 interleaving factors. Fabricated in a 28-nm bulk CMOS process, the presented TI-ADC achieves a Nyquist-frequency signal-to-noise plus distortion ratio (SNDR) and a spurious-free dynamic range (SFDR) of 52.01dB and 58.82dBc at 900MS/s, respectively, with an active area occupation of 0.48 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{\mathbf {2}}$ </tex-math></inline-formula> and similar metrics across all the configurations. Featuring a power dissipation of 42.96mW at 900MS/s, the Nyquist-frequency Schreier figure of merit (FoM) is 152.2dB, whereas the Walden one is 146.6fJ/Conv-step.