3-D CMOS Chip Stacking for Security ICs Featuring Backside Buried Metal Power Delivery Networks With Distributed Capacitance
Kazuki Monta, Hiroki Sonoda, Takaaki Okidono, Yuuki Araga, Naoya Watanabe, H. Shimamoto, Katsuya Kikuchi, Noriyuki Miura, Takuji Miki, Makoto Nagata
Abstract
3-D stacks of complimentary metal-oxide-semiconductor (CMOS) integrated circuit (IC) chips for security applications monolithically embed backside buried metal (BBM) routing with low series impedance and high decoupling capability in a power delivery network (PDN), thanks to distributed capacitances over a full-chip backside area. The 3-D Si demonstrator integrating cryptographic engines was fabricated in a 0.13-μm CMOS technology with post-Si wafer-level BBM Cu processing with 10, 15, and 10 μm of thickness, linewidth, and space, respectively, along with through Si vias (TSVs) with 10 and 40 μm of diameter and depth, respectively. The capacitance of 0.18 nF/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> in the effective backside area of 71 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> suppressed dynamic IR drops in 10% and 59% for the single chip and four chip stack samples, respectively, during the operation of a 3.9 M-gate crypto core at 30 MHz. On-chip power noise monitoring (OCM) was applied in these measurements. The 3-D BBM PDN also effectively reduces power side channel information leakage, which is evaluated by 14× increase in the number of externally observed electromagnetic (EM) noise waveforms to attain the t-test value of larger than 4.5.