HERMES Core – A 14nm CMOS and PCM-based In-Memory Compute Core using an array of 300ps/LSB Linearized CCO-based ADCs and local digital processing
Riduan Khaddam-Aljameh, Miloš Stanisavljević, Jordi Fornt, Geethan Karunaratne, Matthias Bräendli, F. Liu, Abhairaj Singh, Silvia M. Müller, Urs Egger, Αναστάσιος Πετρόπουλος, Theodore Antonakopoulos, Kevin Brew, S. Choi, Kang Min Ok, F. L. Lie, Nicole Saulnier, V. Chan, Ishtiaq Ahsan, Vijay Narayanan, S. R. Nandakumar, Manuel Le Gallo, Pier Andrea Francese, Abu Sebastian, Evangelos Eleftheriou
Abstract
We present a 256×256 in-memory compute (IMC) core designed and fabricated in 14nm CMOS with backend-integrated multi-level phase-change memory (PCM). It comprises 256 linearized current controlled oscillator (CCO)-based ADCs at a compact 4µm pitch and a local digital processing unit performing affine scaling and ReLU operations A novel frequency-linearization technique for CCOs is introduced, leading to accurate on-chip matrix-vector-multiply (MVM) when operating over 1 GHz. Measured classification accuracies on MNIST and CIFAR-10 datasets are presented when two cores are employed for deep learning (DL) inference The measured energy efficiency is 10.5 TOPS/W at a performance density of 1.59 TOPS/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .