Ultrahigh Bias Stability of ALD In<sub>2</sub>O<sub>3</sub> FETs Enabled by High Temperature O<sub>2</sub> Annealing
Zhuocheng Zhang, Zehao Lin, Chang Niu, Mengwei Si, Muhammad A. Alam, Peide D. Ye
Abstract
In this work, we systematically studied the temperature dependent electrical performance of atomic-layer-deposited (ALD) indium oxide $\left(In_{2} O_{3}\right)$ transistors. Both enhancement-mode (E-mode) and depletion-mode (D-mode) $In_{2} O_{3}$ FETs are demonstrated by high temperature O <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> annealing at $400^{\circ} C$ with maximum drain current over $2 mA/ \mu m$, on/off ratio up to 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">9</sup> , highest mobility beyond $100 cm^{2} / V \cdot s$ and lowest subthreshold swing (SS) of 70 mV/dec. High threshold voltage $\left(V_{T}\right)$ stability is achieved in both negative and positive bias stress conditions with minimum threshold voltage shift $\left(\Delta V_{T}\right)$ of -18 mV under gate bias stress of -2 V for 5000 s. Such ultrahigh bias stability can be attributed to the passivation of oxygen vacancies by O <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> annealing. Temperature dependent I-V characteristics as well as bias instability are also comprehensively investigated. The optimized reliability indicates the back-end-of-line (BEOL) compatible ALD $In_{2} O_{3}$ does offer the great potential as the novel competitive channel in monolithic 3 D integration.