A Review of Logarithmic Multiplier Hardware Architectures
M V V Prasad Kantipudi, Vemuri Sailaja, Venkata Kiran Sanipini
Abstract
Multiplication is basics for any arithmetic operations of central processing unit and graphical processing units. Nowadays multipliers are widely used in digital image processing, digital signal processing, network security, and multimedia applications. Therefore, high performance multipliers are mandatory to design and implement fast multimedia devices. Several high-performance multipliers are suggested in the last few decades by researchers such as booth multiplication, wallace tree multiplication, bough wooley multipliers, karatsuba multipliers and logarithmic multipliers. Among the various schemes of multiplication algorithms, logarithmic multiplication is widely used in image processing and multimedia applications due its high performance. This paper analyses the very large-scale integration (VLSI) characteristics of different logarithmic multipliers in terms of speed, power consumption and area utilization. Based on the detailed review, this paper suggests that logarithmic multiplier which uses an approximation-based multiplier by using the concept of double-sided fault distribution is deemed as high-accuracy baseline design for implementing instead of using the Mitchell-based algorithm. This approximation-based design is also suitable for area utilization and power consumption.