GraphClusNet: A Hierarchical Graph Neural Network for Recovered Circuit Netlist Partitioning
Xuenong Hong, Tong Lin, Yiqiong Shi, Bah‐Hwee Gwee
Abstract
Hardware assurance (HA) is imperative to ensure the integrity of integrated circuits (ICs) after manufacturing. To verify the integrity of an IC would require the extraction of relevant functional block of interest through circuit partitioning. This is usually done by converting a recovered circuit netlist into a circuit graph and subsequently performing unsupervised clustering on the graph. However, circuit graphs are difficult to cluster due to the existence of inherent hierarchies and clusters of imbalanced sizes. In this article, we propose a novel hierarchical graph neural network (GNN), termed as GraphClusNet, to perform circuit graph clustering in a multistage process to achieve near-optimal results. We analytically derive a normalized-cut-based loss function, which allows for clusters of imbalanced sizes. We train our GraphClusNet in a multistage hierarchical fashion to regularize intermediate node embedding, which greatly alleviates the oversmoothing effect in deep GNNs. We further propose a multiscale location-based node feature and feature concatenation to provide a good initialization to stabilize the training of our GNN. Based on the experiments of synthetic graphs, we show that our proposed GraphClusNet obtained solutions with <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n-cut</i> values up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\mathbf {65\times }$</tex-math></inline-formula> closer to the global optimum. On FPGA circuit graphs, our proposed GraphClusNet outperformed the reported methods with up to 30% improvement in normalized mutual information for circuit graph clustering.