High-Performance CVD MoS<sub>2</sub> Transistors with Self-Aligned Top-Gate and Bi Contact
Weisheng Li, Dongxu Fan, Liangwei Shao, Futao Huang, Lei Liang, Taotao Li, Yifei Xu, Xuecou Tu, Peng Wang, Zhihao Yu, Yi Shi, Hao Qiu, Xinran Wang
Abstract
We fabricated high-performance MoS <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> FETs featuring large-area CVD MoS <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> channel, self-aligned top-gate, and semi-metallic Bi Ohmic contact. For the first time, semi-metallic Bi was used in the top-gate 2D FET as source/drain contacts to achieve zero Schottky barrier and reduce contact resistance ( <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$R_{\mathrm{C}}$</tex> ). The devices showed <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$I_{\text{ON}}$</tex> of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$680\ \mu \mathrm{A}/\mu \mathrm{m}$</tex> at 60 nm gate length ( <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$L_{\mathrm{g}}$</tex> ) and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$R_{\mathrm{C}}$</tex> of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$280\ \Omega\cdot\mu \mathrm{m}$</tex> , which are the best reported values among top-gate 2D FETs. It is predicted that, by scaling down the gate length to sub-10 nm technology nodes, our proposed top-gate MoS <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> FET technology will meet the requirement of the IRDS 2028 targets of logic transistors.