Minimum Operating Voltage Prediction in Production Test Using Accumulative Learning
Yen-Ting Kuo, Wei-Chen Lin, Chun Chen, Chao-Ho Hsieh, James Chien-Mo Li, Eric Jia-Wei Fang, Sung S.-Y. Hsueh
Abstract
We propose a new methodology to predict minimum operating voltage (V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">min</inf> ) for production chips. In addition, we propose two new key features to improve the prediction accuracy. Our proposed accumulative learning can reduce the impact of lot-to-lot variations. Experimental results on two 7nm industry designs (about 1.2M chips from 142 lots) show that we can achieve above 95% good prediction. Our methodology can save 75% test time compared with traditional testing. To implement this method, we will need to have a separate test flow for the initial training and accumulative training.