A 12-Bit 20-kS/s 640-nW SAR ADC With a VCDL-Based Open-Loop Time-Domain Comparator

Xiaochuan Zhou, Xiaoyan Gui, Marjan Gušev, Nevena Ackovska, Yanlong Zhang, Li Geng

2021IEEE Transactions on Circuits & Systems II Express Briefs34 citationsDOI

Abstract

This brief presents a 12-bit ultra-low-power asynchronous successive approximation register (SAR) analog-to-digital converter (ADC). A voltage-controlled delay line (VCDL) based open-loop time-domain comparator is proposed and analyzed, achieving low noise and ultra-low power performance. By employing the mixed switching scheme, the segmented capacitive digital-to-analog converter (CDAC) arrays as well as the synchronous data-weighted averaging (DWA) calibration block, the proposed SAR ADC can operate from 1.8 V down to 0.8 V at 20–200 kS/s. The designed ADC is fabricated in a 0.18- <inline-formula> <tex-math notation="LaTeX">$\mu {\mathrm{ m}}$ </tex-math></inline-formula> CMOS process and the measurement results show the proposed SAR ADC achieves an SNDR of 65-dB with power consumption of 647 nW from a 0.8 V power supply at 20 kS/s.

Topics & Concepts

Successive approximation ADCComparatorCMOSElectronic engineeringAsynchronous communicationComputer scienceCapacitive sensingBlock (permutation group theory)Analog-to-digital converterPower (physics)VoltageElectrical engineeringEngineeringMathematicsPhysicsTelecommunicationsQuantum mechanicsGeometryAnalog and Mixed-Signal Circuit DesignAdvancements in PLL and VCO TechnologiesCCD and CMOS Imaging Sensors