Current issues and emerging techniques for VLSI testing - A review☆
Garima Thakur, Shruti Jain, Harsh Sohal
Abstract
Circuit designers are always faced with new obstacles as a result of the persistent trend in today's nanoscale technology to follow Moore's law. The complexities inherent in the production process have increased dramatically due to the rapid downscaling of integration. Parallel to this, the complexity and unpredictability of silicon chip flaws have increased, making circuit testing and diagnosis more challenging. The amount of test data has multiplied, and the criteria governing integrated circuit testing have grown both in size and in the complexity of correlation. The modern situation provides a useful framework for investigating novel machine learning-based test solutions. In this paper, the authors examine different recent developments in this developing field in the context of digital logic testing and diagnosis.