A 60-Gb/s 1.2-pJ/bit 1/4-Rate PAM-4 Receiver With a Jitter Compensation CDR
Li Wang, Zhao Zhang, Can Wang, Rehan Azmat, Weimin Shi, C. Patrick Yue
Abstract
This article presents a four-level pulse amplitude modulation (PAM-4) receiver (Rx) with a jitter compensation clock and data recovery (JCCDR) for high-speed retimer application. The JCCDR can attenuate the jitter transfer (JTRAN) from the input PAM-4 signal to the recovered clock and data without sacrificing the jitter tolerance (JTOL) bandwidth. A jitter compensation circuit (JCC) is implemented within the JCCDR to support JTRAN detection, complementary signal generation, and JTRAN attenuation functions. Theoretical analysis is performed to verify the effectiveness and challenges of the proposed method. Prototyped in 40-nm CMOS, the Rx achieves error-free operation with PAM-4 input from 30 to 60 Gb/s. The JCCDR provides an ultralow <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$< -$ </tex-math></inline-formula> 8 dB JTRAN while maintaining a 40-MHz wide JTOL bandwidth with a 0.2-UIPP jitter amplitude. A jitter compensation ratio up to 60% can be supported from dc to 4 MHz.