Characterization of Al<sub>2</sub>O<sub>3</sub>/LaAlO<sub>3</sub>/SiO<sub>2</sub> Gate Stack on 4H-SiC After Post-Deposition Annealing
Linhua Huang, Yong Liu, Chao Xiao, Yixiao Ding, Xin Peng, Yuichi Onozawa, Takashi Tsuji, Naoto Fujishima, J.K.O. Sin
Abstract
We fabricated Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /LaAlO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> (ALS) gate stacks on 4H-SiC, with LaAlO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> (LAO) film being annealed in O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> atmosphere. The ALS gate stack annealed at 700 °C exhibits a much higher breakdown effective electric field ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${E}_{\text {eff}}$ </tex-math></inline-formula> ), which is approximately 1.8 times higher than that of traditional SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> gate oxide. The ALS gate stack also yields a low interface state density ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${D}_{\text {it}}$ </tex-math></inline-formula> ) thanks to the intact LAO film. However, an annealing temperature as high as 800 °C induced traps in the LAO film and deteriorated the SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> –SiC interface. The 700 °C-annealed LAO film with a high dielectric constant ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\kappa $ </tex-math></inline-formula> ) of 14 and a low trap density, coupled with good electrical characteristics, makes it a promising gate dielectric for SiC power metal-oxide-semiconductor (MOS) device applications.