Design of Low Power SRAM Cell with Increased Read and Write Performance for Various Applications
Shrikant Upadhyay, Mohit Kumar, Rakesh Kumar, Nacharam Venkatesh, Sandeep Unam, K Akhita
Abstract
The 16T low-power SRAM is a specific type of memory cell designed to help minimize power consumption and maximize stability for energy-efficient uses. The new design also reduces leakage currents, take care of the read-disturb problem and provide better noise immunity by using extra transistors. Important innovations are read/write decoupling and gated feedback to maintain reliable operations at low voltages. Using high-end instruments like Cadence Virtuoso, 16T SRAM exhibits drastically decreased levels of dynamic and static power without sacrificing performance and therefore are suited for low energy consuming applications in IoT, portable devices etc. In this paper a SRAM with 16T has been analysed in term of read and write and the proposed architecture provide a very efficient output in term of transient and DC response. The main objective of low power circuit is to enhanced the performance of system by providing low power and stabilize energy for various types of applications. Such circuit will really helpful for various devices utilizing low power and helps in saving compared to traditional existing SRAM.