28.1 A Fully Integrated, Domino-Like-Buffered Analog LDO Achieving –28dB Worst-Case Power-Supply Rejection Across the Frequency Spectrum from 10Hz to 1GHz with 50pF On-Chip Capacitance

Abstract

In the design of fully integrated low-dropout (LDO) regulators, minimizing the on-chip output capacitance $\left(C_{L}\right)$ is of utmost importance, as it predominantly contributes to the silicon area overhead. However, reducing C <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</inf> not only compromises the LDO’s feedback stability but also adversely impacts its power-supply rejection (PSR). To avoid the stability issues associated with a small C <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</inf> , many prior works [1–4] have adopted the internal-pole-dominant (IPD) LDO design, where the dominant pole frequency (ω <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gate</inf> ) is situated at an internal node rather than at the output $\left(V_{\text {OUT }}\right)$. As depicted on the left of Fig. 28.1.1, IPD LDOs exhibit superior PSR at low frequencies (termed $\mathrm{PSR}_{\mathrm{LF}}$) owing to their ample DC-loop gain [1, 2]. However, as the frequency surpasses ω <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gate</inf> , the loop gain’s roll-off deteriorates their high-frequency PSR ($PSR_{\mathrm{HF}}$). While supply-ripple-cancellation schemes [3, 4] have been introduced to improve PSR in IPD LDOs, their efficacy might be susceptible to process variations, given that they necessitate accurate and intricate supply-ripple feedforward mechanisms. In contrast to IPD LDOs, output-pole-dominant (OPD) LDOs [5, 6], in which the dominant pole $\left(\omega_{\text {out }}\right)$ is created at $V_{\text {OUT }}$, favor achieving moderate PSR over a wide frequency range. The high C <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</inf> -dominance in OPD LDOs enables the concurrent reduction in both loop gain and output impedance at $\omega \geq \omega_{\text {out }}$, yielding a more uniform $\mathrm{PSR}_{\mathrm{LF}}$. Beyond the unity-gain frequency $\left(\omega_{\mathrm{ugf}}\right), C_{\mathrm{L}}$ functions as a supply-ripple filter, thus guaranteeing an excellent PSR $\mathrm{HF}_{\mathrm{HF}}$. However, OPD LDOs demand a higher frequency for the non-dominant pole $\left(\omega_{2 n d}\right)$ to ensure stability. The top-right of Fig. 28.1.1 shows the insertion of a gate-drive buffer, promoting higher $\omega_{2 n d}$, placed between an error amplifier (EA) and a power PMOS. In this typical design, ω <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">B</inf> and ω <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</inf> , formed at the buffer input and output, respectively, govern $\omega_{2 n d}[\approx \left.\left(\omega_{B} \cdot \omega_{G}\right)^{0.5} / 2\right]$. Enhancing the buffer’s drivability can boost ω <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</inf> due to the reduction in the buffer’s output resistance $\left(R_{\mathrm{B}}\right)$, but it also leads to a decrease in $\omega_{\mathrm{B}}$, attributed to the increased input capacitance $\left(C_{\mathrm{B}}\right)$ of the buffer. This trade-off sets an inherent ceiling on elevating $\omega_{2 n d}$. Consequently, for stability, OPD LDOs still require a considerably large C <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</inf> , depressing $\omega_{\text {out }}\left(\lt \lt\omega_{2 n d}\right)$, at the expense of silicon real estate.

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