Impact of the Self-Heating Effect on Nanosheet Field Effect Transistor Performance
Billel Smaani, Neha Paras, Shiromani Balmukund Rahi, Young Suh Song, Ramakant Yadav, Subham Tayal
Abstract
Nanosheet Field Effect Transistor (NSFET) has emerged as a promising candidate to replace FinFET devices at sub-7nm technology nodes and for different SoC applications. In this work, we have investigated the DC properties of 3D vertically-stacked NSFET including the impact of self-heating effect (SHE) and also influence of geometry scaling. The thermal resistance and the maximum lattice temperature have been analyzed according to the device’s channel number. Also, the distribution of lattice temperature has been exposed. During the 3D investigation, it has been observed that SHE degrades the switching performance and subthreshold swing SS ≈ 22%. Furthermore, it is found that the proposed device is showing improved figure of merits as I ON (∼2.77 × 10 −5 A), I OFF (∼10 −20 A), SS (>60 mV decade −1 ) and I ON /I OFF (∼10 15 ). The DIBL has been reduced by −52% when the NS’s width is ranging from 10 to 5 nm, and increased from 32 to 92 mV V −1 when the gate-length decreases from 14 to 8 nm.